1. Field
Embodiments of the present invention generally relate to register instruction scheduling in order to reduce the overall register usage in a computing system. For instance, embodiments of the present invention can be used to reduce the overall register usage in a compiler-generated executable of a computing system.
2. Background
Computing applications, such as graphics applications, typically employ millions of data-parallel instructions. Oftentimes, the performance of a computing system (e.g., graphics processing unit or central processing unit) is determined by how many instructions can be executed simultaneously, in which the performance can be limited by various hardware resources associated with the computing system. One such hardware resource is the number of registers.
The computing system oftentimes includes a scheduler to manage the usage of its registers. In particular, the scheduler can manage the registers as a pool, where each incoming instruction into the computing system is allocated to one or more registers until the pool of registers is full. Consequently, an overflow of instructions cannot be allocated to a register until another instruction is completed. As computing applications continually evolve and become increasingly complex, thus increasing the number of data-parallel instructions associated with the application, the allocation of instructions to registers and associated compute time related to register allocation adversely affects the performance of the computing system.